Hi, I am Surabhi.
I am an ASIC Design Engineer working on high speed networking silicon and exploring hardware security, especially hardware Trojans, logic locking, and security aware RTL design. I like building small, concrete experiments and sharing what I learn with students and early career engineers.
What I am working on
- Designing and verifying RTL for networking ASICs.
- Building small, reproducible experiments for hardware Trojan behavior and detection.
- Using NEOS based logic locking on simple ISCAS circuits and observing switching activity.
- Preparing talks and material on chip security for student groups and future conferences.
Featured project
Hardware Trojan and Logic Locking Lab Series
A hands on repository with baseline RTL designs, Trojan inserted variants, and experiments on rare trigger Trojans, sequential triggers, logic locking, and basic switching activity observations. The goal is to give students and early engineers simple entry points into chip security.
Tech: Verilog, Icarus Verilog, VCD waveforms, Python scripts, NEOS based logic locking.
Talks and speaking
I have presented technical topics in academic, industry, and community settings, including Cisco internal presentations, USC course projects, and student events.
- USC SWE guest session on moving from USC to an ASIC role and an introduction to chip security.
- Logic locking and hardware Trojan project presentations during my masters at USC.
- Architecture presentations on NoC and processor design, and other course projects.
- Cisco internship summary and innovation challenge presentations.
See all talks on the Talks page.
Writing
I write short guides and explanations on hardware security, RTL concepts, and early career engineering topics. You can find the full list on the Writing page.
A Technical Guide to Logic Locking for Chip Security
- Short explainers on RTL design and verification.
- Walkthroughs of hardware Trojan experiments from my open source repo.
- Notes on ASIC careers and early engineering growth.
I also publish on Medium when I write longer posts.
Latest posts
- Recent Trends in Hardware Security: The Shift from Logic to Architecture (Feb 24, 2026)
- Understanding Rare Nets and Why Trojans Love Them (Dec 7, 2025)
- What Is a Hardware Trojan? (Nov 23, 2025)
See all posts on the Writing page.
About
I work in ASIC design and verification for networking chips, and I am especially interested in how we can make hardware more trustworthy, from RTL all the way to silicon. During my masters at USC I worked on logic locking and hardware Trojan concepts as part of my graduate coursework and projects, and I am now turning those ideas into small, practical experiments and talks.
Contact
The easiest way to reach me is here: