Skills
Technical Skills
Design
- Verilog and synthesizable SystemVerilog
- RTL design, integration, and synthesis
- Static timing analysis (STA)
- Clock domain crossing (CDC) understanding
- Secure and logic locked design concepts
Verification
- Simulation using VCS and Xcelium
- Waveform debug using Verdi
- Emulation experience with Veloce
- DPI and socket based automation
- Basic coverage closure and testbench development
Programming and Scripting
- Python
- C and C++
- Tcl and Perl
- Socket programming
- Basic protocol modeling
- Synopsys Design Compiler
- Synopsys PrimeTime
- SpyGlass
- Cadence Xcelium
- Veloce emulation environment
Domains
- Ethernet MAC
- Packet processing
- CRC logic
- Synthesizable test environments
- Hardware Trojan concepts and logic locking
Soft Skills
- Explaining technical ideas in clear, simple language
- Presenting in academic and industry settings
- Writing beginner friendly technical content
- Supporting early engineers and students
- Leading and moderating group discussions
Areas I Want To Grow In
- Side channel and power based analysis
- Formal verification
- Open source hardware security research
- Teaching chip design and security concepts