Projects

Hardware Trojan and Logic Locking Lab Series

Hands on experiments on Trojan insertion, sequential triggers, switching activity analysis, and logic locking using NEOS.
Repo: Hardware Trojan Lab

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Security-Aware RTL Design for Hardware Trojan Mitigation

Designed and evaluated security-aware RTL modifications to understand how hardware Trojans affect functionality and switching behavior.
Explored simple detection strategies and logic locking based mitigation ideas.
Tech: Verilog, testbenches, waveform analysis

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4-Core Ring Based Multiprocessor

Designed a bidirectional ring NoC router, NIC, and 32-bit CPU as part of a 4-core multiprocessor system.
Performed synthesis and timing analysis at around 250 MHz.
Tech: Verilog RTL, NoC architecture, synthesis

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RISC-V Processor

Implemented a simple 3-stage pipelined RISC-V processor with stall, bypass, and annul logic.
Tech: Verilog RTL

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CMOS SRAM Design

Implemented a 512-bit 6T SRAM array with decoders, sense amps, and a layout optimized for noise margin and delay.
Tech: Cadence Virtuoso, 6T SRAM

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RJ45++ Connector Extension (Cisco Innovation Challenge)

Developed an intelligent RJ45 extension module for cable identification and asset tracking.
Runner-up in Cisco’s company-wide innovation challenge.
Tech: architecture, embedded system behavior

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GitHub Pages Portfolio

This website serves as my speaker and project portfolio.
Repo: Portfolio

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More project write-ups will be added soon.