About Me
I am an ASIC Design Engineer working on high speed networking silicon. My work focuses on RTL design, simulation, and supporting hardware software co design for large scale chips. Alongside my industry work, I explore hardware security topics such as logic locking, switching activity analysis, and simple Trojan insertion experiments.
During my graduate program at USC, I worked on hardware Trojan mitigation and logic locking through several course projects and presentations. I enjoyed presenting these topics and explaining them in a simple way to classmates, which eventually led me to build my current open source Hardware Trojan and Logic Locking Lab Series.
I like supporting students and early engineers through writing and speaking. My past speaking experience includes industry presentations at Cisco, academic presentations at USC, and an upcoming session with USC Society of Women Engineers.
This website collects my projects, talks, experiments, and writing. My goal is to keep learning and help others understand chip design and security a little better.